PicoRV32

PicoRV32 is a small 32-bit RISC-V core with no cache of its own. It reaches the L1.5 through pico_l15_transducer.v and the related files that already exist in OpenPiton. MACE selects it with core="pico", which adds -pico and -rv32_target_triple=riscv64-unknown-elf to the sims command line. The second flag lets the installed riscv64-unknown-elf toolchain assemble RV32 code.

Status

MACE’s loop passes 2x2 and 4x4 PicoRV32 meshes on addi.S, with every tile reaching Hit Good trap, in the runs of the 0.0.1 pre-release. See Results.

Bring-up fixes

OpenPiton’s CI builds PicoRV32 under Verilator but does not run it. Three fixes make it run:

Fix	Where	Effect
Self-boot gate	`piton/design/chip/tile/pico/rtl/picorv32.v` (patch fix 6)	The core’s internal `resetn` only rose on an L15 interrupt that a bare configuration never sends. A `booted` register now lets it start once after reset while keeping its sleep and wake path.
Monitor tracking	`piton/verif/env/manycore/pc_cmp.v.pyv` (patch fix 7)	The monitor’s `active_thread` bit for pico waited on the same interrupt. It now turns on after reset, as Ariane’s block does, so the monitor detects good and bad traps.
BIST self-clear	RTL define `CONFIG_DISABLE_BIST_CLEAR`	OpenPiton’s generic SRAM model (`bram_1rw_wrapper.v`) runs a power-on BIST clear. PicoRV32 boots faster than the other cores, so the clear discards its first memory writes. The define turns the clear off.

Fixes 6 and 7 come from scripts/patch_openpiton.sh. The BIST define is a build option, so a run has to request it:

By hand: PitonConfig(core="pico", config_rtl=("CONFIG_DISABLE_BIST_CLEAR", "MINIMAL_MONITORING")).
Through the loop: the planner emits a CONFIG_RTL: line naming the define for its task. See Planner.

A task builds with its own CONFIG_RTL: flags plus those of every task it depends on, so each pico task needs the define directly or through a dependency.

Workloads

PicoRV32’s OpenPiton integration has an assembler (piton/tools/bin/rv32_as) but no C compiler, and no crt.S or syscalls.c under piton/verif/diag/assembly/include/riscv/pico/. Only assembly workloads such as addi.S run on it. A C workload like barrier_atomic.c never compiles, and every tile idles at its reset vector on an empty memory image.