faultflow¶
faultflow is a gate-level fault simulator and native SAT ATPG engine for post-synthesis netlists produced by Yosys. It grades stuck-at and transition faults, generates test patterns with a built-in SAT-based ATPG, and reports fault coverage against a precisely defined denominator.
It is built as a Python control plane over a C++17 simulation core, with the two joined by a pybind11 bridge. Everyday use is through an interactive Tcl shell; a batch CLI covers the same ground for scripted, one-shot runs.
Note
faultflow targets Unix-like systems only (Linux, or Windows via WSL). There is no native Windows build. See Installation.
What it does¶
Stuck-at and transition fault grading on flat, post-synthesis gate-level netlists, using a 64-lane bit-parallel simulation engine cross-checked against a scalar golden reference.
Native SAT ATPG (CaDiCaL) that produces simulator-verified test vectors, with a progressive loop, fault collapsing, and reverse-order test-set compaction.
Sequential and scan support: edge-triggered flip-flops, asynchronous set/reset, scan-chain insertion, and scan ATPG.
IEEE 1500 wrapper test and hierarchy: INTEST/EXTEST boundary test, a native shiftable WBR, and hierarchical block-to-SoC coverage aggregation.
Two PDKs: SkyWater Sky130 HD (default) and OSU035, driven by JSON cell maps.
Deterministic coverage reporting with an explicit, auditable denominator.
flowchart LR
A[Verilog RTL] --> B[Yosys synthesis]
B -->|JSON netlist| C[faultflow core]
B -->|gate-level Verilog| E[iverilog verification]
C --> D[coverage.rpt + SQLite campaign DB]
E -.optional gate.-> D
Getting started¶
Build the C++ core and set up the Python environment on Linux or WSL.
Run your first fault-simulation campaign on the c17 benchmark from the
interactive Tcl shell.
Stuck-at faults, ATPG, the coverage denominator, and scan in plain terms.
The batch ff.py / faultflow CLI, for scripted and one-shot runs.
Learn more¶
About faultflow — the feature matrix and a high-level tour.
Architecture overview — the three-layer IR and the simulation engine.
Testing & verification — how correctness is established and kept that way (the golden-reference cross-check).
Benchmarks — ISCAS-85/89, transition faults, and PicoRV32a results.
Roadmap — what is planned next.