OpenTestability Documentation
Welcome to the OpenTestability comprehensive documentation. This tool provides professional circuit testability analysis with multiple algorithms and metrics.
Navigation
User Guide
Test Point Insertion (TPI)
Testability Analysis
- COP Analysis Guide
- SCOAP Metrics
- Verilog Auto-Pipeline
- Reconvergence Integration
- Reconvergence Quickstart
Reference
Algorithms
API Reference
Resources
Overview
OpenTestability is a comprehensive framework for automated test point insertion and circuit testability analysis, featuring:
Core Capabilities
- Test Point Insertion (TPI): Automated design-for-testability (DFT) implementation
- Observation points for internal signal visibility
- Control points for enhanced signal controllability
- Metrics-driven test point selection
- Industry-standard Verilog output compatible with EDA tools
- Advanced Testability Analysis: Professional circuit analysis capabilities
- COP (Controllability Observability Program) with probability-based metrics
- SCOAP (Sandia Controllability Observability Analysis Program) metrics
- Automatic reconvergence correlation detection
- Integrated parallel computation for large circuits
- Streamlined Workflow: One-command analysis from Verilog to results
- Direct Verilog file processing
- Automatic pipeline execution
- Professional tool environment
- CC0/CC1 controllability metrics
- CO observability metrics
- Modular 7-component architecture
- Integrated Reconvergence: Automatic fanout reconvergence detection
- Basic algorithm: O(n²) complexity, simple path tracing
- Simple algorithm: O(n² log n) complexity, 98% accuracy with pruning
- Advanced algorithm: O(n³) complexity, exhaustive correlation detection
- Parallel Computation: Automatic parallelization for circuits >100,000 gates
- 3-4x speedup on multi-core systems
- Transparent activation based on circuit size
- Automatic dependency management
Additional Features
- Verilog Netlist Parsing: Parse gate-level netlists from synthesis tools (Synopsys, Cadence)
- DAG Construction: Build directed acyclic graphs for topological analysis
- Visualization: Generate circuit graphs using Graphviz
- Professional CLI: Interactive tool environment similar to commercial EDA tools
What’s New
Test Point Insertion
Automated test point insertion for improved testability:
opentest> tpi -i netlist.json -m metrics.json -o design_tp.v
This automatically:
- Analyzes testability metrics to find hard-to-test signals
- Designs observation and control points
- Inserts test points into the netlist
- Generates enhanced Verilog with DFT interface
Verilog Auto-Pipeline
Run complete analysis with a single command:
opentest> auto-cop designs/circuit.v results/analysis
This automatically:
- Parses Verilog netlist
- Builds DAG structure
- Detects reconvergence (simple algorithm)
- Calculates COP metrics
- Outputs JSON results
COP (Controllability Observability Program)
New probability-based testability analysis:
- Controllability: P(node=0) and P(node=1) using gate probability models
-
Observability: P(output changes node changes) with Bayesian networks - Correlation-Aware: Automatic adjustment for reconvergent fanout
- Parallel Support: Leverages multiprocessing for large circuits
Example usage:
opentest> cop circuit_dag.json results/cop_analysis
See the COP Algorithm Guide and COP API Reference for details.
Integrated Reconvergence Detection
All analysis commands now support automatic reconvergence detection:
opentest> scoap circuit_dag.json results/scoap --reconvergence simple
opentest> cop circuit_dag.json results/cop --reconvergence advanced
Choose from:
basic: Fast O(n²) path tracingsimple: Balanced O(n² log n) with 98% accuracy (recommended)advanced: Exhaustive O(n³) correlation detection
Parallel Computation
Automatic parallelization activates for circuits >100k gates:
from opentestability.core.cop import run_cop
# Automatically uses parallel processing if circuit is large
results = run_cop(dag_data, enable_reconvergence=True)
Quick Start
1. Install OpenTestability
pip install opentestability
2. Run COP Analysis on Verilog
opentest> auto-cop designs/my_circuit.v results/cop_analysis
3. View Results
opentest> cat results/cop_analysis.json
See Getting Started for detailed instructions.
Architecture
OpenTestability
├── Core Analysis Engines
│ ├── Test Point Insertion (TPI)
│ │ ├── main.py - TPI orchestrator and CLI entry point
│ │ ├── analyzer.py - Metrics analysis and candidate ranking
│ │ ├── designer.py - Test point design with loop prevention
│ │ ├── inserter.py - Transactional netlist modification
│ │ ├── verilog_writer.py - Verilog-2001 code generation
│ │ ├── validator.py - Result validation and reporting
│ │ ├── state.py - State machine and checkpoint management
│ │ └── tech_library.py - Sky130 cell library parsing
│ ├── COP (Controllability Observability Program)
│ │ ├── run_cop.py - Main analysis orchestrator
│ │ ├── controllability.py - Probabilistic controllability (P0, P1)
│ │ ├── observability.py - Bayesian observability analysis
│ │ ├── gate_logic.py - Probability models for all gate types
│ │ ├── reconvergence.py - Correlation detection and adjustment
│ │ ├── parallel.py - Multiprocessing support
│ │ └── output.py - Results formatting and export
│ ├── SCOAP (Sandia Controllability Observability Analysis)
│ │ ├── CC0/CC1 controllability metrics
│ │ ├── CO observability metrics
│ │ └── Modular 7-component architecture
│ ├── DAG Builder
│ │ ├── Directed Acyclic Graph construction
│ │ └── Topological sorting and validation
│ └── Reconvergence Analyzers
│ ├── Basic Algorithm (O(n²))
│ ├── Simple Algorithm (O(n² log n), 98% accuracy)
│ ├── Advanced Algorithm (O(n³))
│ └── Integration Module (automatic detection)
├── Parsers
│ ├── Verilog Parser (pyverilog-based)
│ ├── JSON Converter
│ └── Auto-Pipeline Support
├── Visualization
│ └── Graph Renderer (Graphviz)
└── CLI Tool Environment
├── Interactive Command Shell
└── Commands: parse, build-dag, scoap, cop, tpi, auto-cop, auto-scoap,
test-reconv, visualize, help, exit
Key Concepts
COP vs SCOAP
- SCOAP: Integer-based complexity metrics (lower is more testable)
- CC0: Controllability to 0
- CC1: Controllability to 1
- CO: Observability
- COP: Probability-based metrics (higher is more testable)
- P0: Probability of controlling to 0
- P1: Probability of controlling to 1
- Obs: Probability of observing changes
When to Use COP
- When you need probabilistic test pattern effectiveness
- For correlation-aware analysis in circuits with reconvergent fanout
- When analyzing large circuits (benefits from parallelization)
- For integration with statistical ATPG tools
When to Use SCOAP
- For traditional testability metrics compatible with existing tools
- When integer-based scoring is preferred
- For faster computation on smaller circuits
Documentation Sections
For New Users
- Getting Started - Installation and setup
- Test Point Insertion Guide - Primary feature: Automated DFT
- TPI Examples - Step-by-step TPI workflows
- Testability Analysis - COP and SCOAP metrics
- Command Reference - Complete CLI documentation
For COP Users
- COP Algorithm Guide - Mathematical foundations
- COP API Reference - Complete API documentation
- Reconvergence Integration - Correlation analysis
- Reconvergence Quickstart - 5-minute guide
For Developers
- API Documentation - Complete API reference
- COP Modules - COP implementation details
- Core Modules - SCOAP and DAG APIs
- Parser API - Verilog parsing interface
- Contributing Guide
For Researchers
- Algorithm Details - SCOAP, COP, and reconvergence algorithms
- Parallel SCOAP - Parallelization strategies
- Performance Benchmarks
Support
- Issues: Report bugs or request features
- Discussions: Ask questions and share ideas
- Contributing: Contribution guidelines
- Changelog: Release history
Citation
If you use OpenTestability in your research, please cite:
@software{opentestability,
title = {OpenTestability: Professional Circuit Testability Analysis},
author = {Rana Umar Nadeem},
year = {2026},
version = {0.0.1},
url = {https://github.com/ranaumarnadeem/OpenTestability}
}
License
This project is licensed under the Apache-2.0 License - see the LICENSE file for details.