TPI inserts observation and control logic so hard-to-test internal signals become easier to control and observe.

What gets added

Depending on mode and selected points, the generated design can include:

• control inputs such as test_mode and tp_ctrl_*
• observation outputs such as tp_obs_*
• global enable ports such as tp_obs_en and tp_ctrl_en

Minimal workflow

Genus mode

# 1) Generate metrics
python3 opentest --genus cop -i designs/priority_enc.v -j

# 2) Insert test points
python3 opentest --genus tpi -i <netlist.json> -m <metrics.json> -t 50 -n 10 -v

Yosys mode

python3 opentest --yosys analyze_and_add_tp -i <design.json> --scoap -t 50 -m 10 -v

Key parameters

Simulation checklist

Drive all DFT/test inputs in your testbench:

reg test_mode;
reg tp_ctrl_0;
reg tp_ctrl_1;

initial begin
    test_mode = 1'b0;
    tp_ctrl_0 = 1'b0;
    tp_ctrl_1 = 1'b0;
end

Also ensure your circuit reset sequence initializes all state elements.

Expected behavior

1. With test_mode = 0, functional outputs should match the original design.
2. Observation outputs should mirror internal nodes without destabilizing normal logic.
3. Verbose mode should produce per-run logs and reports under results/.

Troubleshooting

• If inserted ports show X, check that every new test input is explicitly driven.
• If TPI inserts fewer points than expected, reduce threshold or increase max points.
• If mode errors appear, confirm your input format matches --genus or --yosys expectations.

Related pages

1. Getting Started
2. Examples
3. Command Reference