Docs / Genus (Legacy Verilog) Mode

Genus mode is the original Verilog-input workflow — historically called genus mode because the gate-level netlists came from Cadence Genus / Synopsys DC. It gave you full, stage-by-stage control: parse a Verilog netlist, convert it, build a DAG, run COP/SCOAP, and insert test points, emitting enhanced Verilog.

Genus mode is not part of the current release. It was removed before 0.0.1, when OpenTestability moved to a Yosys-JSON-only flow. The complete implementation — every command below — is preserved on the legacy-genus branch. This page documents that branch so the workflow is not lost.

Getting genus mode

git checkout legacy-genus

On that branch, every command is invoked with the --genus flag:

python3 opentest --genus <command> [options]
python3 opentest --genus help

The tool guards the mode: a Verilog file in Yosys mode (or Yosys JSON in genus mode) is rejected with a message telling you which flag to restart with.

What genus mode is for

Use --genus when you want explicit control over each stage of the Verilog pipeline rather than a single end-to-end run.

Typical scope:

Command flow

Verilog -> parse -> convert -> dag -> cop / scoap -> tpi -> enhanced Verilog

Analysis commands (scoap, cop, …) given a Verilog file can auto-pipeline the earlier stages for you; the individual commands exist for when you want to run — or inspect — a single stage.

Commands

Command Purpose
parse Parse a Verilog netlist into the intermediate text format
convert Convert a parsed text netlist to JSON
dag Build the DAG representation from a netlist
scoap SCOAP testability metrics (Verilog or parsed input)
cop COP probabilistic testability metrics (Verilog or parsed input)
auto-cop COP with automatic reconvergence detection + parallel computation
auto-scoap SCOAP with automatic reconvergence detection + parallel computation
reconv / simple / advanced Reconvergence detection variants
compare Compare reconvergence algorithms on a design
visualize Generate a Graphviz visualization of the circuit graph
tpi Insert test points from a netlist + a metrics file
analyze_and_add_tp End-to-end analysis plus test-point insertion
status Show current project status
help Show help text (help <command> for per-command detail)

Options

Option Meaning
-i, --input Input Verilog / parsed netlist / JSON file
-o, --output Output file name
-m Metrics file (for tpi); also max test points on some commands
-n Max test points to insert (tpi)
-t, --threshold TPI difficulty threshold
-a, --algorithm Reconvergence algorithm: basic, simple, advanced, dominator
-r, --reconvergence Enable reconvergence-aware analysis
-w, --workers Worker count for the parallel auto-* commands
-j, --json Write JSON output where supported
-v, --verbose Detailed analysis logs and reports

Test-point count uses -n (or -m) depending on the command — check python3 opentest --genus help <command>.

Recipes

# Help, per command
python3 opentest --genus help
python3 opentest --genus help tpi

# Stage by stage
python3 opentest --genus parse -i designs/priority_enc.v
python3 opentest --genus convert -i <parsed.txt>
python3 opentest --genus dag -i <netlist.json>

# Metrics (Verilog input auto-pipelines the earlier stages)
python3 opentest --genus scoap -i designs/priority_enc.v -j
python3 opentest --genus cop -i designs/priority_enc.v -j

# Metrics with automatic reconvergence + parallelism
python3 opentest --genus auto-scoap -i <netlist.json> -w 4 -v

# Test-point insertion from an explicit metrics file
python3 opentest --genus tpi -i <netlist.json> -m <metrics.json> -t 50 -n 10 -v

# End to end (analyze + insert), emitting enhanced Verilog
python3 opentest --genus analyze_and_add_tp -i designs/priority_enc.v --scoap -t 50 -m 10 -v

# Reconvergence exploration
python3 opentest --genus reconv -i <netlist.json>
python3 opentest --genus compare -i <netlist.json>
python3 opentest --genus visualize -i <netlist.json>

Output and reports

Resolve paths through the project’s output utilities, not hardcoded directories.

Common pitfalls

Moving to the current (Yosys) flow

The current release ingests Yosys JSON only. To run a Verilog design on it, convert with Yosys first, then use the --yosys commands:

yosys -p "read_verilog design.v; synth; write_json design.json"
python3 opentest analyze_and_add_tp -i design.json --scoap -t 50 -m 10 -v
  1. Getting Started
  2. Command Reference
  3. Test Point Insertion Guide
  4. SCOAP API